1. Field of the Invention
The present invention relates to an A/D converter capable of being employed in a solid-state image sensing device represented by a CMOS image sensor, a solid-state image sensing device, and a camera system.
2. Description of the Related Art
For complementary metal-oxide semiconductor (CMOS) image sensors, the same manufacturing process as that for typical CMOS integrated circuits can be adopted. The CMOS image sensor can be driven with a sole power supply. Further, analog circuits and logical circuits can be integrated into the same chip using a CMOS process.
Therefore, the CMOS image sensor has plural merits including the merit of helping decrease the number of peripheral ICs.
As for charge-coupled device (CCD) output circuits, a mainstream CCD output circuit provides an output on a one channel using a floating diffusion (FD) amplifier which has a floating diffusion layer.
In contrast, a mainstream CMOS image sensor has the FD amplifiers disposed in respective pixels, and provides a column-parallel output by selecting a certain row in an array of pixels and simultaneously reading pixels in the row in the direction of columns.
This is because since it is hard to obtain a sufficient driving ability from the FD amplifiers disposed in the pixels, it is necessary to decrease a data rate. From this viewpoint, parallel processing is thought to be advantageous.
As for a pixel signal reading (output) circuit to be employed in a column-parallel output type. CMOS image sensor, various circuits have been proposed.
One of the most advanced types is such that analog-to-digital converters (hereinafter, abbreviated as ADC) are disposed in respective columns and pixel signals are fetched in the form of digital signals.
The column-parallel output type CMOS image sensor including the ADC has been disclosed in, for example, “An Integrated 800×600 CMOS Image System” written by W. Yang et al. (ISSCC Digest of Technical Papers, pp. 304-305, February, 1999) (non-patent document 1) and JP-A-2005-278135 (patent document 1).
FIG. 1 is a block diagram showing an example of the configuration of a column-parallel ADC inclusive solid-state image sensing device (CMOS image sensor).
The solid-state image sensing device 1 includes, as shown in FIG. 1, a pixel array 2, a vertical scan circuit, a horizontal transfer scan circuit 4, and a group of column processing circuits 5 that is a group of ADC.
Further, the solid-state image sensing device 1 includes a digital-to-analog converter (hereinafter, abbreviated as DAC) 6 and an amplification circuit (S/A) 7.
The pixel array 2 has unit pixels 21, each of which includes a photodiode (photoelectric converter) and an intra-pixel amplifier, arranged in the form of a matrix.
The group of column processing circuits 5 has plural column processing circuits 51, each of which serves as an ADC, arrayed in columns.
Each of the column processing circuits (ADC) 51 includes a comparator 51-1 that compares an analog signal, which is obtained from one of pixels in each row over a vertical signal line, with a reference voltage Vslop which is a ramp wave (RAMP) obtained by changing a reference voltage produced by the DAC 6, stepwise.
Further, each of the column processing circuits 51 includes a counter 51-2 that counts up so as to measure the comparison time taken by the comparator 51-1, and a latch (memory) 51-3 that holds a result of counting.
The column processing circuits 51 have an n-bit digital signal converting capability, and are disposed on respective vertical signal lines (column lines) 8-1 to 8-8, whereby column-parallel ADC blocks are constructed.
The output terminals of the memories 51-3 are connected to a horizontal transfer line 9 whose bit width is, for example, 2n.
2n amplification circuits 7 which are arranged correspondingly to the horizontal transfer line 9 is disposed.
FIG. 2 is a timing chart for the circuits shown in FIG. 1.
In each of the column processing circuits (ADC) 51, an analog signal (potential Vsl) read onto the vertical signal line 8 is compared with a reference voltage Vslop (a wave that varies linearly with a certain slope) by the comparator 51-1 disposed in each column.
At this time, the counter 51-2 counts up until the level of the analog potential Vsl crosses the level of the reference voltage Vslop and the output of the comparator 51-1 is reversed. The potential (analog signal) Vsl on the vertical signal line is converted into a digital signal (A/D converted).
The A/D conversion is performed twice with respect to one time of reading.
During the first A/D conversion, a reset level (P-phase level) attained in the unit pixel 21 is read onto the vertical signal line 8 (any of the vertical signal lines 8-1 to 8-n), and then A/D converted.
The P-phase level or the reset level is affected with a variance among pixels.
During the second A/D conversion, the level of a signal photoelectrically converted in each unit pixel 21 (D-phase level) is read onto the vertical signal line 8 (any of the vertical signal lines 8-1 to 8-n), and then A/D converted.
The D-phase level is also affected with the variance among pixels. Subtraction of the P-phase level from the D-phase level is executed in order to achieve correlated double sampling (CDS).
A signal converted into a digital signal is recorded in each of the memories 51-3. The digital signals are sequentially read from the memories into the amplification circuit 7 over the horizontal transfer line 9 by the horizontal (column) scan circuit 4, and finally outputted.
Thus, column-parallel output processing is carried out.